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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003, zarlink semiconductor inc. all rights reserved. features ? quad band gsm (800/900/1800/1900 mhz) compatible ? dual band is136 (800/1900 mhz) compatible ? gprs class 12 and edge capable ? fully integrated dual band transceiver ? receive - if to baseband i and q ? transmit - baseband i / q to rf ? integrated filters ? fm demodulator ? rf and if synthesizers ? fully programmable via serial bus ? 3 volt operation ? small scale package applications ? gait is136/gsm/edge mobile telephones ? dual band (850/pcs1900) tdma/amps mobile telephones ? cellular 850mhz tdma/amps mobile telephones ? pcs1900 tdma mobile telephones ? 2.5g world phones - quad band (850/900/1800/1900) ? cellular telematic systems description the zl20250 is a fully integrated transceiver for multimode is136/gsm/gprs/edge handsets. the dual if inputs to the receive path are amplified and down-converted to baseband i and q signals. gain control and baseband filtering are provided. a fm demodulator is also provided where amps compatibility is required. the transmit path consists of a quadrature modulator, gain control at if and up-conversion to rf. dual band rf outputs are provided. zl20250 also includes a fractional n rf synthesizer and two if synthesizers to provide all local oscillator signals required. flexible programming is provided via a 3 wire serial bus. additional control pins allow accurate timing control when switching between modes. september 2003 ordering information zl20250/lce (tubes) 56 pin qfn zl20250/lcf (tape and reel) 56 pin qfn -40 c to +85 c zl20250 2.5g multimode transceiver data sheet figure 1 - block diagram rx vhf pll serial interface control fm demod iq mod uhf pll tx vhf pll rx i rx q fm rssi tx i tx q gsm/edge is136 uhf vco 900 mhz tx 1900 mhz tx tx if filter (opt) 90 uhf lo o/p lock det
zl20250 data sheet 2 zarlink semiconductor inc. package diagram figure 2 - zl20250 package diagram sdat sclk slatch tcxo vcc uhf pll uhf cp 900 lo out 1900 lo out resetb enable1 900 lo in vcc uhf lo tx 900 tx deg900 tx deg1900 tx 1900 enable2 tx filt in+ tx filt in- vcc tx tx q- tx filt out+ tx filt out- tx q+ vcc control if1 in+ if1 in- if0 in+ if0 in- rx gain vcc rx pll rx vco+ fm out rx i- rx i+ rx vco- rx q- rx q+ rssi rx cp vcc vhf cp lock det tx rxb tx cp tx i- tx i+ iset vcc tx pll tx vco- vcc uhf lo out tx vco+ vcc tx rf 1900 lo in tx gain vcc rx fm fb mgcx01 zl20250
zl20250 data sheet 3 zarlink semiconductor inc. pin description table no pin name type description 1 sdat input serial interface - data 2 sclk input serial interface - clock 3 slatch input serial interface - latch 4 tcxo input reference input from tcxo 5 vcc uhf pll power power 6 uhf cp output uhf pll charge pump output 7 vcc uhf lo out power power to lo output stages 8 900 lo out output 900 mhz buffered lo output to external receiver mixer 9 1900 lo out output 1900 mhz buffered lo output to external receiver mixer 10 resetb input reset (active low) 11 enable1 input mode control 12 900 lo in input 900 mhz lo input 13 vcc uhf lo power power to uhf lo input stage 14 1900 lo in input 1900 mhz lo input 15 vcc tx rf power power to transmit rf output stages 16 tx 900 output 900 mhz transmit output 17 tx deg900 degeneration for 900 mhz output 18 tx deg1900 degeneration for 1900 mhz output 19 tx 1900 output 1900 mhz transmit output 20 enable2 input mode control 21 tx gain input transmit gain control 22 tx filt in+ input input from transmit if filter (optional) 23 tx filt in- input 24 vcc tx power power to transmit stages 25 tx filt out+ output output to transmit if filter (optional) 26 tx filt out- output 27 tx q+ input q transmit signal from baseband 28 tx q- input 29 tx vco+ transmit oscillator tank circuit 30 tx vco- 31 vcc tx pll power power to transmit vhf pll 32 tx i+ input i transmit signal from baseband 33 tx i- input 34 tx rxb input transmit / receive control 35 tx cp output transmit vhf pll charge pump output 36 lock det output pll lock detect output 37 iset connect 50 kohm resistor to ground to set internal reference current 38 vcc vhf cp power power to vhf charge pump outputs
zl20250 data sheet 4 zarlink semiconductor inc. 39 rx cp output receive vhf pll charge pump output 40 rssi output rssi output 41 rx q+ output baseband q signal 42 rx q- output 43 rx i+ output baseband i signal 44 rx i- output 45 fm out output demodulated fm output 46 fm fb feedback to fm output stage 47 rx vco- receive second lo oscillator tank circuit 48 rx vco+ 49 vcc rx pll power power to receive vhf pll. connect to vcc through 10 ohm resistor 50 vcc rx power power to receive stages 51 rx gain input receive gain control 52 if0 in- input if input (0) 53 if0 in+ input gsm 54 if1 in- input if input (1) 55 if1 in+ input is136 input 56 vcc control power power to serial interface logic pin description table (continued) no pin name type description
zl20250 data sheet table of contents 5 zarlink semiconductor inc. 1.0 general description ........................................................................................................ ................................. 8 1.1 receive path ............................................................................................................... ................................ 9 1.1.1 is136.................................................................................................................... .............................. 9 1.1.2 amps fm.................................................................................................................. ....................... 11 1.1.3 gsm ...................................................................................................................... ........................... 14 1.2 transmit................................................................................................................... .................................. 16 1.3 uhf lo and frequency doubler............................................................................................... ................ 19 1.4 uhf frequency synthesizer .................................................................................................. ................... 19 1.5 vhf frequency synthesizer.................................................................................................. .................... 22 1.6 internal clock generation.................................................................................................. ........................ 23 1.7 vhf vco.................................................................................................................... ............................... 23 1.8 power supply connections ................................................................................................... .................... 24 2.0 programming and control .................................................................................................... ........................ 25 2.1 power control registers - address 0 to 3 ................................................................................... .............. 25 2.1.1 power control modes - tdma (gsm and is136) ............................................................................ 27 2.1.2 power control modes - amps ............................................................................................... .......... 28 2.2 operating register address 4 ............................................................................................... .................... 29 2.3 synthesizer register - address 5 ........................................................................................... ................... 33 2.3.1 uhf pll and lo........................................................................................................... ................... 33 2.3.2 uhf pll charge pump current .............................................................................................. ........ 34 2.3.3 receive lo set up ........................................................................................................ .................. 34 2.3.4 transmit lo set up ....................................................................................................... .................. 35 2.4 control register - address 6 ............................................................................................... ...................... 35 2.4.1 is136 baseband gain ...................................................................................................... ................ 35 2.4.2 tcxo reference selection................................................................................................ ............. 36 2.4.3 discriminator output filtering........................................................................................... ................ 36 2.4.4 transmit baseband gain................................................................................................... ............... 37 2.4.5 mode control............................................................................................................. ....................... 37 2.5 gsm/edge baseband control register - address 7............................................................................. ... 37 2.5.1 q channel gain adjust .................................................................................................... ................ 38 2.5.2 baseband offset correction............................................................................................... .............. 38 2.6 test mode register - address 8............................................................................................. ................... 38 2.7 uhf pll divider programming register - address 9 ........................................................................... .... 39 2.8 uhf pll reference divider and fractional n programming register - address 10 ................................ 39 2.9 receive vhf pll divider programming register - address 11 ............................................................... 39 2.10 receive vhf pll reference divider programming register - address 12............................................ 40 2.11 transmit vhf pll divider programming register - address 13 ............................................................ 40 2.12 transmit vhf pll reference divider programming register address 14 ............................................. 40 2.13 pll lock detect & fractional n compensation programming register address 15 .............................. 40 2.13.1 fractional n compensation............................................................................................... ............. 41 2.13.2 pll lock detect counters................................................................................................ ............... 41 3.0 absolute maximum ratings ................................................................................................... ....................... 41 4.0 operating conditions ....................................................................................................... ............................. 41 5.0 electrical characteristics ................................................................................................. ............................. 43 6.0 typical performance curves ................................................................................................. ....................... 51 6.1 receive.................................................................................................................... .................................. 51 6.2 transmit................................................................................................................... .................................. 52
zl20250 data sheet list of figures 6 zarlink semiconductor inc. figure 1 - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - zl20250 package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 3 - zl20250 detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4 - is136 receiver signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5 - amps receive signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6 - gsm receive signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7 - transmit path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8 - external transmit if filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9 - uhf synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10 - count sequence for uhf pll with 4 modulus prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11 - uhf synthesizer - fractional n operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12 - vhf frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13 - typical vco tank circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 14 - serial bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15 - transmit output stage current versus gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
zl20250 data sheet list of tables 7 zarlink semiconductor inc. table 1 - is136 receive gain and filter distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2 - amps fm receive gain and filter distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3 - gsm receive gain and filter distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4 - transmit circuit blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
zl20250 data sheet 8 zarlink semiconductor inc. 1.0 general description a detailed block diagram is shown in figure 3. this shows the receive and transmit paths plus the lo generation circuitry. control is via a serial bus with the addition of direct inputs to control receive and transmit modes and optimize power consumption. figure 3 - zl20250 detailed block diagram rssi rx q+ rx q? /2 /2 serial interface amps demod. and rssi lo select and doubler 60khz dc offset pll pll synth programming pll /2 /2 control 43 44 mux mux rx i+ rx i? 45 46 41 42 40 fm out fm fb 32 33 27 28 1 2 3 tx i+ tx i? tx q+ tx q? sdat sclk slatch 56 34 20 11 10 21 26 25 22 23 vcc control tx rxb enable2 enable1 resetb 24 vcc tx tx gain tx filt out? tx filt out+ tx filt in+ tx filt in? 15 17 vcc tx rf tx deg900 18 tx deg1900 19 16 tx 900 tx 1900 53 52 51 55 54 9 8 12 14 6 if0 in+ if0 in? rx gain if1 in+ if1 in? 1900 lo out 900 lo out 900 lo in 1900 lo in uhf cp vcc uhf lo 13 29 35 4 39 48 31 38 49 47 37 30 tx vco? tx vco+ tx cp rx cp rx vco+ tcxo rx vco? i set vcc rx pll vcc tx pll vcc vhf cp 7 50 vcc uhf lo out vcc rx 5 vcc uhf pll 36 lock det mux option tank circuit tank circuit control n /2 loop filter loop filter loop filter option dc offset
zl20250 data sheet 9 zarlink semiconductor inc. 1.1 receive path there are two if inputs which will receive an input signal from is136/amps and gsm if filters. the differential input stages are identical and are followed by an agc amplifier. gain control is provided from an external analogue voltage. after the agc amplifier the signal is then down-converted either to a low if frequency or baseband and the signal flow then depends on the mode selected. all internal signals are differential. the lo frequency for the down conversion is derived from an on chip oscillator and pll. the lo frequency can be programmed to be either oscillator frequency divided by 2 or 4. when in divide by 2 mode a dll (delay locked loop) circuit can be selected to maintain accurate quadrature. it is particularly important to have good quadrature in is136/amps modes using a low if frequency, to achieve the required image rejection in conjunction with the following polyphase bandpass filter. it is also possible to programme high side or low lo injection. each receive mode will now be described in more detail 1.1.1 is136 the is136 receive signal path is shown in detail in figure 4 and performance for each stage is summarized in the following table. the output of the agc amplifier is down-converted using a quadrature mixer to a low if of 60khz. high side or low side lo injection can be selected. the in phase (i) and quadrature (q) signals at 60 khz are then passed through anti alias filter stage to remove any high frequency signals prior to subsequent sampling. the 60 khz if signals are then fed into a switched capacitor polyphase bandpass filter which not only provides filtering but also provides image rejection. this switched capacitor filter provides very stable performance and no calibration is required. after the bandpass filter the 60 khz if signal is further amplified and then mixed down to baseband i and q signals. additional filtering is required at baseband to remove spurii from the down-converter. this filtering is provide in two stages, the first stage is a switched capacitor filter with the second stage being a smoothing filter to remove clock breakthrough from the preceding switched capacitor filter. the differential baseband outputs can then be fed directly into analogue to digital converters on a baseband processor. circuit block gain (db) filter bandwidth (if applicable) description if input (if0) 26 max differential if input stage agc amplifier agc amplifier - gain control range 90db quadrature down-converter 47 down-conversion to 60khz if anti-alias filter 230 khz low pass butterworth (n= 3) band pass filter +/- 20 khz switched capacitor polyphase chebyshev. also provides typically 30 db image rejection. centre frequency = 60 khz. clock frequencies 1.44 mhz and 720 khz. gain stage baseband down-converter 7 down conversion to baseband i and q signals baseband filter 1 37.5 khz switched capacitor low pass chebyshev. clock frequency = 240 khz baseband filter 2 60 khz smoothing filter. low pass butterworth table 1 - is136 receive gain and filter distribution
zl20250 data sheet 10 zarlink semiconductor inc. figure 4 - is136 receiver signal flow baseband filter 1 mx mx fm discriminator quadrature rx vhf pll div2 /div4 loop filter tank circuit if input agc amplifier quadrature downconverter receive baseband receive vhf vco recieve vhf pll if0 if1 i q rssi offset i offset q anti alias filter anti alias filter band pass filter baseband filter 1 baseband filter 2 baseband filter 2 limiter rssi rssi 60 khz gain
zl20250 data sheet 11 zarlink semiconductor inc. 1.1.2 amps fm fm demodulation can be performed using the i and q baseband signals if supported by the baseband. however the zl20250 also contains an fm demodulator, the amps receive signal path using this mode is shown in detail in figure 5 and performance for each stage is summarized in the following table. the signal path is initially the same as for is136 with the down conversion to 60 khz and channel filtering in the bandpass filter. in fm mode however, the baseband i and q output stages are disabled, and the 60 khz if signal from the bandpass filter is input to a limiting amplifier and fm discriminator. the fm discriminator consists of a shift register acting as a delay line. the output of the discriminator is a digital signal which must then be filtered to recover the audio signal. the discriminator output is therefore routed through the baseband i and q filters. the default condition is to use the cascaded i and q smoothing filters (baseband filter 2) with the cut-off frequency set to 30khz. this connection is automatically selected when programming fm mode. there is an option to use the cascaded switched capacitor filters (baseband filter 1) with the cut off frequency set to 25 khz to provide extra filtering. these filters are selected using the pdf and lpc bits in control register 6 and are inserted between the smoothing filters as shown in figure 5. the final output stage uses external feedback components to provide a bandpass filter with a bandwidth of at least 300 hz to 10 khz to cover the demodulated audio and control signals. the feedback components can be modified to change the output level to optimise compatibility with baseband. a rssi output is provided. this is a full wave rectified output of the 60 khz if and therefore has a high 120 khz content. this requires an external low pass filter - typically 10kohm and 2.7nf. there is a trade-off between settling circuit block gain (db) filter bandwidth (if applicable) description if input (if0) 26 max differential if input stage agc amplifier agc amplifier - gain control range 90db. includes if input stage gain. quadrature down-converter 73 down-conversion to 60khz if anti-alias filter 230 khz low pass butterworth band pass filter +/- 16 khz switched capacitor polyphase chebyshev. also provides typically 30db image rejection. centre frequency = 60 khz. clock frequency 1.44 mhz and 720 khz. limiter provides limited output to discriminator. also provides rssi output. fm discriminator digital fm discriminator baseband filter 2 (i channel) 30 khz smoothing filter. low pass butterworth. provides filtering of fm discriminator output. baseband filter 1 (i channel) 25 khz switched capacitor low pass chebyshev. clock frequency = 240 khz. provides additional filtering of discriminator output. selected using pdf and lpc bits baseband filter 1 (q channel) 25 khz switched capacitor low pass chebyshev. clock frequency = 240 khz. provides additional filtering of discriminator output. selected using pdf and lpc bits baseband filter 2 (q channel) 60khz smoothing filter. low pass butterworth. provides filtering of fm discriminator output. fm output 30khz configured using external components as bandpass filter. table 2 - amps fm receive gain and filter distribution
zl20250 data sheet 12 zarlink semiconductor inc. time and filtering. this is different to conventional rssi circuits which operate at typically 450 khz which is much easier to filter. although the amps receive path includes a limiting amplifier, gain control is also required. this is because the band pass filter has limited dynamic range (50db). at low signal levels the agc should be set to 1.6 volts to set the gain 20db below maximum to obtain optimum signal handling and noise performance. at higher signal levels the gain setting should be reduced to maintain the rssi level approximately 10db below maximum. gain control would be provided by the baseband controller which would also monitor the rssi level. fine gain control is not required and can be implemented in large steps eg 20db, allowing the use of a relatively slow gain control loop giving optimum performance under fading conditions.
zl20250 data sheet 13 zarlink semiconductor inc. figure 5 - amps receive signal flow anti- alias filter anti alias filter band pass filter baseband filter 1 baseband filter 1 baseband filter 2 baseband filter 2 mx mx limiter rssi fm discriminator quadrature rx vhf pll div2 /div4 loop filter tank circuit if input agc amplifier quadrature downconverter receive baseband receive vhf vco rssi recieve vhf pll if0 if1 i q fm out fm fb 60 khz rssi offset i offset q gain
zl20250 data sheet 14 zarlink semiconductor inc. 1.1.3 gsm the gsm receive signal path is shown in detail in figure 6 and performance for each stage is summarized in the following table. in gsm mode the bandpass filter and is136 baseband stages are disabled. after passing through the agc amplifier the signal is mixed down to baseband i and q signals rather than to a low if. the baseband signal must be dc coupled and this can introduce a dc offset in the output, which may vary with different gain settings. the zl20250 therefore includes the facility to correct the dc offset for each channel using an 8 bit offset correction word that must be supplied by the baseband via the serial bus. gsm baseband gain can be programmed via serial bus. reducing the baseband gain can be used to improve output signal to noise ratio. the if gain should be increased to mainatin the total overall gain. in practice a gain reduction of 6 or 9 db would give optimum performance circuit block gain (db) filter bandwidth (if applicable) description if input (if0) differential if input stage agc amplifier 26 max agc amplifier - gain control range 90db. includes if input stage gain. quadrature down-converter 54 down-conversion to baseband anti-alias filter 230 khz low pass butterworth. provides channel filtering in gsm/edge mode baseband gain baseband gain with offset correction. nominal gain is 35 db and can be reduced in 3 db steps to 14 db table 3 - gsm receive gain and filter distribution
zl20250 data sheet 15 zarlink semiconductor inc. figure 6 - gsm receive signal flow anti alias filter anti alias filter band pass filter baseband filter 1 baseband filter 1 baseband filter 2 baseband filter 2 mx mx limiter rssi fm discriminator quadrature rx vhf pll div2 /div4 loop filter tank circuit if input agc amplifier quadrature downconverter receive baseband receive vhf vco rssi recieve vhf pll if0 if1 i q 60 khz rssi offset i offset q gain
zl20250 data sheet 16 zarlink semiconductor inc. 1.2 transmit transmit operation is similar for all modes and a detailed diagram is shown in figure 7. this diagram also shows the uhf lo generation circuit blocks. a summary of the characteristics of the transmit path circuit blocks are given in the table below. all circuit blocks are differential with the exception of the transmit rf outputs. differential baseband transmit i and q signals from a baseband processor are input to the zl20250. the baseband signals are passed through filters - the filter bandwidth is selected for the appropriate mode i.e. is136 or gsm. a quadrature modulator modulates these baseband signals on to the transmit if which is typically around 200 mhz. this modulated if signal is passed through an on chip low pass filter which removes harmonics of the if and then into a gain controlled amplifier. this amplifier is controlled by an external analogue signal and provides greater than 60db gain control the output of the gain controlled amplifier can then be up-converted to rf or alternatively the output can be sent to an off chip filter to provide further filtering and removal of noise before up-conversion. this filter is a parallel tuned circuit as shown in figure 8. the choice of component values is dependent on the if frequency being used. the filter output is then fed back on chip to the up-converter. a ssb mixer is used for the up-conversion to remove the unwanted image. high side or low side lo injection can be selected a buffer amplifier after the up-conversion provides a further 9 db gain control in 3 db increments. this gain is programmable via the serial bus and can be used to optimize noise and linearity performance in particular applications. finally there are two rf output stages for 900 mhz and 1900 mhz frequency bands. each rf output is single ended and requires a simple matching network. the supply current of the output stages is automatically reduced at low transmit gain control voltages improving the efficiency of the output buffer at low output power levels. the supply current of the output buffer can also be controlled via the serial bus. this allows the supply current to be reduced which is particularly useful when using amps or gsm where the linearity performance is less critical. the fm modulation for amps can be done using i,q modulation if available. alternatively fm modulation can be applied direct to the transmit if vco. the loop bandwidth for the transmit vhf pll should be low ( ~100 hz) to ensure the pll does not remove the modulation. a dc voltage should be applied across the tx i+, tx i- and the tx q+, tx q- inputs to switch the modulator and generate an if carrier signal. with a baseband gain of 0db a dc voltage of at least 1.5 volts should be applied; a lower voltage can be used with the baseband gain increased to compensate. it is assumed that this bias can be provided by the baseband however if this is not possible then the simplest solution is to connect 200kohm resistors between i+, q+ inputs and vcc and 200kohm resistors between i+,q- inputs and circuit block gain (db) bandwidth (if applicable) description reconstruction filters 0 -12 is136/amps 12.5 khz gsm 100 khz baseband input stage. gain is programmable in 3 db steps from 0 to 12 db. filter bandwidth is selected for is136/amps or gsm. there is also a by-pass mode so that the baseband i and q signal can go direct to the modulator quadrature modulator generates a modulated if signal transmit if 400 mhz provides gain control at if frequency. this stage also includes a low pass filter to remove harmonics and spurii from modulator output. this stage also includes a buffered if output which can be used with an external if filter. up-converter ssb up-converter to rf frequency. the if path includes phase shift networks for the up-converter. this stage also includes the input circuit from the optional external if filter transmit rf the 900 mhz and 1900 mhz rf stages each consist of 2 stages. the first stage gain be set from -6 to +3 db in 3 db steps. output stage current is controlled by agc signal to reduce current consumption at low output power levels. each output stage requires an external degeneration inductor table 4 - transmit circuit blocks
zl20250 data sheet 17 zarlink semiconductor inc. ground assuming the transmit outputs from the baseband are in a high impedance state in amps mode. these resistors do produce a small dc offset in tdma mode however this is insignificant if the output impedance of baseband transmit outputs is less than 1 kohm.as the fm modulation is applied direct to the vco in this mode and is external to the zl20250, any necessary filtering of the fm signal must be provided externally.
zl20250 data sheet 18 zarlink semiconductor inc. figure 7 - transmit path baseband transmit filter quadrature tx vhf pll div2 / div4 loop filter tank circuit transmit rf transmit vhf vco transmit vhf pll tx 1900 tx 900 tx i+/- tx q+/- low pass filter baseband transmit filter + /4 - /4 quadrature tx deg1900 tx deg900 uhf pll loop filter uhf synthesiser frequency doubler 900mhz vco 1900mhz vco 1900 lo in 900 lo in uhf cp 1900 lo out 900 lo out transmit reconstruction filters uhf lo input buffer uhf lo buffer transmitter upconverter if input transmit uhf lo transmit if transmit quadrature modulator tx vco+/- tx cp optional external transmit if filter mux mux mux mux optional by-pass mode tx filt out +/- tx filt in +/- mux
zl20250 data sheet 19 zarlink semiconductor inc. figure 8 - external transmit if filter 1.3 uhf lo and frequency doubler figure 8 also shows the uhf lo buffering and frequency doubler. the zl20250 is designed to operate either with separate external uhf vcos for the 900 and 1900 mhz frequency bands, or alternatively a single 900 mhz vco can be used with the on-chip frequency doubler providing the lo for the 1900 mhz band. a uhf synthesizer is included. the input to the uhf synthesizer will normally be the active uhf lo signal, however when using the frequency doubler mode for 1900 mhz lo generation, the synthesizer input can be selected to be either the frequency doubler output or the 900 mhz input lo signal. the uhf lo input buffer minimizes any load pulling effects on the uhf vco when internal modes are switched. uhf lo output buffers are also provided. these can be used to drive an external mixer for the receive section. if not required these buffers can be powered down. 1.4 uhf frequency synthesizer a fractional n uhf synthesizer is included on the zl20250 to provide lo signals for the transmit up-converter and the external receive rf down-converters. the uhf synthesizer operates with an external vco. a block diagram of the synthesizer is shown in figure 9. . figure 9 - uhf synthesizer reference counter 14 bit quad modulus prescaler 64/65/72/73 m counter 13 bit b 3 bit a 4 bit fractional n counter fractional n scaling dac fractional n compensation dac phase detector charge pump lock detect tcxo uhf lo frac n compensation 8 bits uhf cp +1 +8 +1 5 bits
zl20250 data sheet 20 zarlink semiconductor inc. the synthesizer uses a 4 modulus prescaler with an 'm' counter and 'a' and 'b' swallow counters together with a fractional n counter in the uhf counter allowing maximum flexibility. the reference counter is a simple 14 bit counter. all counter values are programmed via the serial bus and programming details are shown in the programming section. each of the counters operates as count down. at the start of a count the counters are loaded with their respective values. the initial prescaler ratio is dependent on the values loaded into the a and b counters; when both the a and b counters reach zero the prescaler ratio is 64 and then remains until the m counter reaches zero. the complete process is then repeated. this can be shown in a simple example where m = 9, a = 4 and b = 2 which gives a total divide ratio of 596. the count sequence is shown in figure 10. figure 10 - count sequence for uhf pll with 4 modulus prescaler at the start of the count sequence the '+1' and '+8' controls to the prescaler are both asserted and the prescaler ratio is 73. after 2 cycles only the '+1' control is asserted and the divide ratio is 65. after a further 2 cycles the a counter reaches zero as well and the prescaler ratio is 64 for the remainder of the count sequence. at the end of the sequence all counters are reloaded and the sequence repeats. the total divide ratio (n) for this type of counter is given by n = 64*m + 8*b + a m is always greater then a or b a value of a = 0 does not support fractional n operation. valid values of a are 1 to 8. the values of m, b and a can be easily calculated from the total divide ratio as shown below. m = int ((n - 1)/64) b = int (((n - 1) - 64*m)/8) a = n - 64*m - 8*b the value of m must always be greater than a or b. the maximum value of b is 7. 9 m counter a counter b counter prescaler +1 prescaler +8 prescaler 8 7 6 5 4 3 2 1 9 8 4 3 2 1 0 0 0 0 0 4 3 2 1 0 0 0 0 0 0 0 2 1 73 73 65 65 64 64 64 64 64 73 73
zl20250 data sheet 21 zarlink semiconductor inc. the uhf synthesizer also includes a fractional n capability which allows the use of higher comparison frequencies but maintain narrow channel spacing. the use of higher comparison frequencies allows faster loop settling and reduces comparison spur level. this is particularly important in tdma mode where settling times of < 1.5 ms are required and still obtain good spur performance. fractional n allows the use of non-integer divide ratios. for example if the total divide ratio is n + 1/5 the counter will divide by n for 4 count cycles and n+1 on the fifth cycle giving the required total divide ratio over five cycles. the zl20250 can use 5,8,13 or 20 as the fractional denominator (also referred to as the fractional modulus) allowing maximum flexibility in the choice of comparison frequencies. an extra counter - fractional n counter - is required. the input to this counter is from the m counter output. the fractional n modulus can be programmed to be 5,8,13, or 20. each output pulse from the m counter will increment the fractional n divided by the required fractional numerator. for example if the fraction is 2/5 then the fractional n counter will increment by 2 for each output pulse from the m counter. when the fractional n counter overflows the a counter is incremented by 1, thus generating an additional '+1' count sequence. an example is shown in figure 11 for a divide ratio of 596+2/5. the values for m, a, b are calculated using the integer value (596) as in the previous example. the fractional denominator is programmed as 5 and the fractional numerator as 2. at the end of the first count cycle (596) the fractional counter is incremented to 2. at the end of the third count cycle the fractional n counter overflows, incrementing the a counter by 1 which gives a subsequent count cycle of 597. after five count cycles the sequence repeats with a total count of 2982 over the five count cycle giving a mean value of 596 + 2/5. figure 11 - uhf synthesizer - fractional n operation a result of this count sequence is that the output phase of the total counter changes through the count cycle, which causes the output pulse from the phase detector, and therefore the charge pump, to vary. this would cause large fractional spurs on the synthesizer output. these spurs can be compensated by applying a current pulse with the opposite polarity to the charge pump output. this compensation pulse has a fixed width of two reference clock (tcxo) periods; the amplitude is proportional to the value in the fractional n counter. the correction current is scaled by a 8 bit compensation dac, with an externally provided input from the serial bus. this allows performance to be optimized in a given application. 596 596 597 596 2 4 1 3 597 596 2 0 0 total count cycle count value fractional n counter initial a counter value 4 4 5 4 4 5
zl20250 data sheet 22 zarlink semiconductor inc. the compensation value can be calculated from the following formula: comp value = 255 - int((icp * ftcxo)/(0.0245 * 6 * mod *fvco)) where icp = charge pump current (ua) ftcxo = reference frequency mod = fractional modulus fvco = uhf vco frequency the synthesizer provides a lock detect output. when the output pulse from the phase detector is less than half a reference clock period an in-lock signal is generated. these in-lock signals then clock a 4 bit counter into which a threshold value has been programmed. when the required number of successive in-lock pulses have been generated the lock detect output is set. the zl20250 has a single lock detect output pin for the uhf synthesizer and vhf synthesizers. the lock detect signal is asserted when all active synthesizers are in lock. if a synthesizer has not been enabled in the power control registers then that synthesizer will be inactive and will have no effect on the lock detect output. 1.5 vhf frequency synthesizer the zl20250 includes two vhf synthesizers to generate the second lo for the receiver and the transmit if. they operate with their respective on-chip vhf vco's and off-chip loop filters. the tank circuits and tuning components for the vco's are also off chip. the two synthesizers are identical and are shown in figure 12. figure 12 - vhf frequency synthesizer the synthesizer uses a 2 modulus 16/17 prescaler with an 'm' counter and an 'a' swallow counter. this allows maximum flexibility when using this synthesizer. the reference counter is a simple 14 bit counter. all counter values are programmed via the serial bus and programming details are shown in the programming section. both counters operate as count down. at the start of a count the counters are loaded with their respective values. the initial reference counter 14 bit dual modulus prescaler 16/17 m counter 13 bit a 4 bit phase detector charge pump lock detect tcxo vhf lo vhf cp +1
zl20250 data sheet 23 zarlink semiconductor inc. prescaler ratio is 17 assuming a > 0; when the a counter reaches zero the prescaler ratio is 16 until the m counter reaches zero. the complete process is then repeated. the total divide ratio (n) for this type of counter is given by n = 16*m + a m is always greater then a the values of m and a can be easily calculated from the total divide ratio n. m = int (n/16) a = n - 16*m the maximum value for a is 15 and m must always be greater than a. the vhf plls do not have fractional n capability however it is recommended that thay are operated at as high a comparison frequency as allowed by the chosen frequency plan to minimise spurs levels. both vhf synthesizers have lock detection circuits. these operate in the same way as described for the uhf synthesizer. 1.6 internal clock generation zl20250 can use 14.4 mhz or 19.44mhz reference frequency (standard for is136), or 13 mhz or 26 mhz (standard for gsm). the appropriate reference must be programmed via the serial bus. the clock signals for the switched capacitor filters and fm demodulator are generated from the reference tcxo signal. the internal divide ratios are switched to give the optimum ratio. for dual mode applications (gsm/is136) a 13 mhz or 26 mhz reference should be used. this will give a small error in the switched capactor clock frequency used for is136 but has negligible effect on performance. 1.7 vhf vco zl20200 has two vhf vcos which operate with the vhf plls to provide the if lo signals for both receive and transmit if signals. the oscillators are a differential design and require an external tank circuit. a basic circuit with varactor is shown in figure 13. it is recommended to include series resistors (eg 43 ohms) in each arm of the tank circuit to prevent any spurious high frequency oscillation due to parasitic capacitances. figure 13 - typical vco tank circuit nm 33n 18p 18p 43r 43r 10k 10k from pll loop filter vco+ vco-
zl20250 data sheet 24 zarlink semiconductor inc. 1.8 power supply connections the circuit blocks within zl20250 have separate supply connections to minimize interaction between circuit blocks. details are shown in the earlier ?pin names? section. these supplies are also grouped to allow different groups of supply pins to be connected to separate supplies for example, receive or transmit. these groups are shown below: the lo out and tx 900/1900 pins require bias and are normally connected to vcc through an inductor. all supply pins within a group must be powered together. each group of pins can be powered up independent of the other groups. vcc ? control supply pin no. pin name 56 vcc control vcc ? txrx common (synth) pin no. pin name 5 vcc uhf pll 7 vcc uhf lo out 13 vcc uhf lo 38 vcc vhf cp 8 900 lo out 9 1900 lo out vcc ? rx pin no. pin name 49 vcc rx pll 50 vcc rx vcc ? tx pin no. pin name 15 vcc tx rf 24 vcc tx 31 vcc tx pll 16 tx 900 19 tx 1900
zl20250 data sheet 25 zarlink semiconductor inc. 2.0 programming and control programming via the serial bus is via 24 bit words with a 4 bit address as shown below bit23 (msb) is loaded first. bits 3:0 are used as address bits for the control registers. details of serial bus timing are shown in figure 14. figure 14 - serial bus timing 2.1 power control registers - address 0 to 3 these registers are used in conjunction with the tx rxb and enable1 and enable2 control pins to power up the required sections of the device for any required mode. this enables power consumption to be optimized under all conditions. figures 4 - 7, which show the receive and transmit paths in detail, show which sections are powered up by each control bit. the assignment is common for each of the registers 0 to 3 and is shown below. 23222120191817171514131211109876543210 data address bit circuit section 23 not used 22 receive baseband section 21 uhf lo buffer 20 receive vhf vco sclk sdat slatch bit 23 bit 22 bit 21 bit 0 t1 t2 t3 t4 t5 t6 enable1/2 t7
zl20250 data sheet 26 zarlink semiconductor inc. note 1: if a bit is set to logic 1 then that circuit section is powered on. note 2: uhf lo input (bit 9) must be enabled for transmit uhf lo (bit 10), uhf synthesizer (bit 19) and uhf lo buffer (bit 21) t o be active. the 4 registers address 0 to 3 are assigned as follows: 19 uhf synthesizer 18 receive rssi circuit 17 not used 16 receive quadrature down-converter 15 receive vhf pll 14 receive if input 13 receive agc amplifier 12 transmit reconstruction filters 11 transmit rf 10 transmit uhf lo 9 uhf lo input buffer 8 transmit if 7 transmit quadrature modulator 6 transmit vhf pll 5 transmit vhf vco 4 transmit up-converter if input register address register name description 0 receive all circuit blocks required in receive mode should be set to 1. this register will be selected when tx rxb is low. no circuits will be actually powered up if enable1 and enable 2 are both low. 1 transmit transmit register all circuit blocks required in transmit mode should be set to 1. in duplex modes e.g. amps then both receive and transmit circuits must be selected. this register will be selected when tx rxb is high. no circuits will be actually powered up if enable1 and enable 2 are both low 2 enable1 configuration this register determines which circuit sections are powered up when enable1 is high. the contents of this register are logical anded with the contents of the receive or transmit register as selected by tx rxb input. 3 enable2 configuration this register determines which circuit sections are powered up when enable2 is high. the contents of this register are logical anded with the contents of the receive or transmit register as selected by tx rxb input. bit circuit section
zl20250 data sheet 27 zarlink semiconductor inc. a feature of this programming approach is that once a phone operating mode has been selected and set up via the serial bus, all power control can then be via the tx rxb, enable1 and enable2 control pins. alternatively full power control is possible via the 3 wire serial bus without the use of any external control pins. if enable1 and enable2 are both low then the device is in sleep mode. no circuits will be enabled unless either enable1 or enable2 are high regardless of the contents of the receive and transmit registers. an example of how these control bits can be used, is that the oscillators and pll circuits can be powered up and allowed to settle prior to powering up the complete transmit or receive path. in the case of the receive path the uhf synthesizer, uhf lo input buffer, uhf lo buffer and receive vhf vco, receive vhf pll bits would be set in the enable1 configuration register. the enable2 configuration register would contain these bits plus the remainder of the receive path bits, receive if input, receive agc amplifier, receive quadrature down-converter and receive baseband section. this is demonstrated in the following examples. 2.1.1 power control modes - tdma (gsm and is136) in a tdma system the transceiver will either operate in receive only, or transmit only mode. it is assumed that an interim power on state will be used during which the oscillators and plls will be set up, and allowed to settle prior to activating the full signal path. the suggested programming for the power control registers (0 - 3) is shown in the table below. bit circuit section receive addr 0 transmit addr 1 enable 1 config. addr 2 enable 2 config. addr 3 comments 23 not used 0 0 0 0 22 receive baseband section 1 0 0 1 21 uhf lo buffer 0 0 0 0 note 1 20 receive vhf vco 1 0 1 1 19 uhf synthesizer 1 1 1 1 18 receive rssi circuit 0 0 0 0 note 2 17 not used 0 0 0 0 16 receive quadrature down-converter 1 0 0 1 15 receive vhf pll 1 0 1 1 14 receive if input 1 0 0 1 13 receive agc amplifier 1 0 0 1 12 transmit reconstruction filters 0 1 0 1 11 transmit rf 0 1 0 1 10 transmit uhf lo 0 1 0 1 9 uhf lo input buffer 1 1 1 1 8transmit if 0 1 0 1 7 transmit quadrature modulator 0 1 0 1 6 transmit vhf pll 0 1 1 1
zl20250 data sheet 28 zarlink semiconductor inc. note 1: not required if driving external receive mixer direct from uhf vco. note 2: can be used for is136 if required. the receive register contains all bits required when in receive mode: the transmit register contains all bits required in transmit mode. the enable1 configuration register contains all bits required to power up oscillators and synthesizers in both receive and transmit mode. the enable2 configuration register contains all bits required to power up the complete receive and transmit modes (this register can be set to all '1's if preferred). the following words should therefore be programmed on the serial bus (hex format): receive register (0) 59e200 transmit register (1) 081ff1 enable1 config. register (2) 188262 enable2 config. register (3) 59fff3 2.1.2 power control modes - amps when operating in amps mode the zl20250 will operate in either receive only or duplex. the enable registers should therefore be programmed as shown below. 5 transmit vhf vco 0 1 1 1 4 transmit up-converter if input 0 1 0 1 bit circuit section receive addr 0 transmit addr 1 enable 1 config. addr 2 enable 2 config. addr 3 comments 23 not used 0 0 0 0 22 receive baseband section 1 1 0 1 21 uhf lo buffer 0 0 0 0 note 1 20 receive vhf vco 1 1 1 1 19 uhf synthesizer 1 1 1 1 18 receive rssi circuit 1 1 0 1 17 not used 0 0 0 0 16 receive quadrature down-converter 1 1 0 1 15 receive vhf pll 1 1 1 1 14 receive if input 1 1 0 1 13 receive agc amplifier 1 1 0 1 12 transmit reconstruction filters 0 1 0 1 11 transmit rf 0 1 0 1 10 transmit uhf lo 0 1 0 1 9 uhf lo input buffer 1 1 1 1 8 transmit if 0 1 0 1 bit circuit section receive addr 0 transmit addr 1 enable 1 config. addr 2 enable 2 config. addr 3 comments
zl20250 data sheet 29 zarlink semiconductor inc. note 1: not required if driving external receive mixer direct from uhf vco. the receive register contains all bits required when in receive mode: the transmit register contains all bits required in duplex mode. the enable1 configuration register contains all bits required to power up oscillators and synthesizers in both receive and duplex mode. the enable2 configuration register contains all bits required to power up the complete receive and duplex modes (this register can be set to all '1's if preferred). the following words should therefore be programmed on the serial bus (hex format): receive register (0) 5de200 transmit register (1) 5dfff1 enable1 config. register (2) 188262 enable2 config. register (3) 5dfff3 2.2 operating register address 4 this registers selects internal setups for example is136 or gsm. the bits are assigned for control of receive and transmit bits as shown below: the function of the receive bits is shown below: bit 23 rx<7> is only applicable when vco divide by 2 mode is selected in register 5. 7 transmit quadrature modulator 0 1 0 1 6 transmit vhf pll 0 1 1 1 5 transmit vhf vco 0 1 1 1 4 transmit up-converter if input 0 1 0 1 23 22 21 20 19 18 17 16 15 14 13 12 11 109876543210 rx<7:0> tx <11:0> 0100 receive set up transmit set up address register bit no. control bit action if '0' action if '1' 23 rx<7> receive dll disabled receive dll enabled 22 rx<6> bandpass filter bw = +/- 20 khz bandpass filter bw = +/- 16 khz 21 rx<5> gsm filters active receive gsm filters bypassed 20 rx<4> lo output = 900 mhz lo output = 1900 mhz 19 rx<3> receive output dc bias (i/q) = 1.25 v receive output dc bias (i/q) = vcc/2 18 rx<2> is136 mode if1 input enabled gsm mode if0 input enabled 17 rx<1> amps is136 16 rx<0> not used not used bit circuit section receive addr 0 transmit addr 1 enable 1 config. addr 2 enable 2 config. addr 3 comments
zl20250 data sheet 30 zarlink semiconductor inc. the function of the transmit bits is shown below: control bits tx<11:4> allow optimization of the transmit output stage. this allows variation of the decrease in supply current with decreasing agc voltage and also allows optimization depending on output power and linearity requirements. figure 15 shows the variation of output stage supply current with agc voltage and the programmable characteristics. the maximum current, agc threshold and slope can be programmed. the minimum current is not programmable. tx<11:10> (bits 15,14) allow the gain of the transmit output stage to be varied in 3 db steps as shown in the table below: register bit no. control bit action if '0' action if '1' 15 tx<11> transmit output stage gain control 14 tx<10> 13 tx<9> control of rf transmit output stage current with vga control voltage. nominal value for tx<11:4> is 101010 12 tx<8> 11 tx<7> 10 tx<6> 9tx<5> 8tx<4> 7 tx<3> 900 mhz output 1900mhz output 6 tx<2> internal external transmit if filter 5 tx<1> is136 baseband filters gsm/edge baseband filters 4 tx<0> transmit baseband filters selected transmit baseband filters by-passed tx<11> tx<10> gain (db) 00-6 01-3 10nominal 11+3
zl20250 data sheet 31 zarlink semiconductor inc. figure 15 - transmit output stage current versus gain control tx<9:8> (bits 13:12) control the agc voltage (vth) at which the output stage current starts reducing. typical values are shown in the table below: tx<7:6> (bits 11,10) control the rate of current reduction as shown in figure 15. typical vales are shown in the below: tx<9> tx<8> vth (v) 0 0 1.09 0 1 1.25 1 0 1.48 1 1 2.81 tx<7> tx<6> slope (ma/v) 00 8.5 01 10.5 10 12.0 11 14.0 vagc icc imax imin vth slope
zl20250 data sheet 32 zarlink semiconductor inc. tx<5:4> (bits 9:8) adjust the maximum current (imax) of the transmit output stage. the gain of the output stage is not changed. typical values are shown in the table below: using these controls allows the performance of the output stage to be optimized under various conditions; for example, current cant can be reduced if non-linear operation is required. the nominal value recommended for tx<11:4> is 10101010. an example of setting up the control register (address 4) for various systems is shown below: tx<5> tx<4> current 0025% 0150% 10nominal 1 1 150% bit name gsm (850) gsm (1900) is136 (900) is136 (1900) amps comments 23rx<7>00000 22rx<6>00001 21rx<5>00000 20rx<4>01010 19rx<3>00000 note 1 18rx<2>11000 17rx<1>00110 16rx<0>00111 15tx<11>11111 14tx<10>00000 13tx<9>11111 12tx<8>00000 11tx<7>11111 10tx<6>00000 9tx<5>11111 8tx<4>00000 7tx<3>01010 6tx<2>01010 note 2
zl20250 data sheet 33 zarlink semiconductor inc. note 1: the setting for rx<3> is dependent on the optimum common mode input voltage of the analog to digital converter in the baseband. note 2: selects external transmit if filter if used. the following hex words are therefore recommended for the control register (address 4): gsm (850) 04aa24 gsm (1900) 4aae4 is136 (900) 03aa04 is136 (1900) 13aac4 amps 41aa04 2.3 synthesizer register - address 5 this register sets up lo options for receive and transmit and also uhf synthesizer set up. bits 23,17,14 are also used for uhf pll and lo set up. bits 16,15 are not used and should be set to zero. 2.3.1 uhf pll and lo note 1: bit 14 is only effective if 1900 mhz mode has been selected (register 4 bit 7). note 2: bit 23 is only effective if 1900 mhz mode has been selected (register 4 bit 7) and the uhf frequency doubler selected (register 5 bit 14). this control allows the use of the doubled frequency to be used as the input to the uhf pll. note 3: fractional n denominator note 4: bits 8,7 select the fractional n denominator for the uhf pll as shown below: 5tx<1>11000 4tx<0>00000 232221201918 17 16 15 14 131211109876543210 0 0101 ui rx lo2 set up uc dl ud tx lo set up uhf pll set up address register bit no. action if '0' action if '1' 23 uhf pll input = 900 mhz uhf pll input = 1900 mhz 17 fractional n compensation selected 14 uhf doubler selected 8 fractional n denominator - see table below 7 6 not used - set to 0 5 uhf pll charge pump current - see table below 4 bit name gsm (850) gsm (1900) is136 (900) is136 (1900) amps comments
zl20250 data sheet 34 zarlink semiconductor inc. 2.3.2 uhf pll charge pump current bits 5,4 select the charge pump current for the uhf pll as shown below: 2.3.3 receive lo set up bits 19,18 select the charge pump current for the receive vhf pll as shown below: <8> <7> frac n denom. 00 5 01 8 10 13 11 20 <5> <4> current (ma) 00 1.00 01 0.50 10 0.25 1 1 0.125 register bit no. action if '0' action if '1' 22 high side rx second lo injection low side rx second lo injection 21 rx second lo = vco/2 rx second lo = vco/4 20 rx lo phase detector polarity normal rx lo phase detector polarity inverted 19 receive vhf pll charge pump current - see table below 18 <19> <18> current (ma) 0 0 1.00 0 1 0.50 1 0 0.25 1 1 0.125
zl20250 data sheet 35 zarlink semiconductor inc. 2.3.4 transmit lo set up bits 10,9 select the charge pump current for the receive vhf pll as shown below: 2.4 control register - address 6 2.4.1 is136 baseband gain bits 22:21 can be used to vary the gain of the baseband output stages in is136 mode only. the gain of the 60 khz if stage preceding the baseband mixer is also varied so that the overall gain of the device can be maintained if required. the nominal gain is 20 db and the recommended setting is bbg<1:0> = 11 to minimize output dc offsets. register bit no. action if '0' action if '1' 15 transmit dll disabled transmit dll enabled 13 low side tx up-converter lo injection high side tx up-converter lo injection 12 tx second lo = vco/2 tx second lo = vco/4 11 tx lo phase detector polarity normal tx lo phase detector polarity inverted 10 transmit vhf pll charge pump current - see table below 9 <10> <9> current (ma) 00 1.00 01 0.50 10 0.25 11 0.125 23222120191817161514131211109876543210 00 0110 bbg tcxo pdf lpc tx gain r mode control address bbg<1> bit 22 bbg<0> bit 21 if gain (db) baseband gain (db) overall gain (db) 0014620 0117623 1017017 1120020
zl20250 data sheet 36 zarlink semiconductor inc. 2.4.2 tcxo reference selection bits 20:19 are used to set the device to the required tcxo reference frequency. 2.4.3 discriminator output filtering bits 17:14 set up on chip filtering of the fm output signal and are therefore only used in amps mode. two cascaded filters can be selected and the bandwidth can be set to 25 or 37.5 khz cut-off. bits 17,16 (pdf) select the filters and bits 15,14 set the cutoff frequency. in gsm and is136 modes bits <17:14> should be set to 0000. it is recommended that if the additional discriminator filtering is required in amps mode then both filters should be used with 25 khz bandwidth, i.e. bits<17:14> should be set 1111. tcxo<1> bit 20 tcxo<0> bit 19 tcxo frequency (mhz) 00 13.0 01 14.4 10 19.44 11 26.0 <17> <16> <15> <14> filter selection 0 0 x x no filters 0 1 x x filter 1 selected 1 0 x x filter 2 selected 1 1 x x filters 1 and 2 selected x x 0 0 both filters 37.5 khz x x 0 1 filter 1 25khz, filter 2 37.5khz x x 1 0 filter 1 37.5 khz, filter 2 25 khz x x 1 1 both filters 25khz
zl20250 data sheet 37 zarlink semiconductor inc. 2.4.4 transmit baseband gain bits 13:11 set the transmit baseband gain as shown below: 2.4.5 mode control bit 10 resets the contents of all registers to '0'. after the reset is complete bit 10 is also reset to '0'. bits 9:4 allow txrxb, enable1 and enable2 to be programmed by either the external pins or via the serial bus. this allows mode control to be either via the external pins or the serial bus. the default state is using the external pins as this allows more accurate timing of power control. bits 9:7 can only be used if the appropriate bits 6:4 have been set to disable the external pins. if serial mode has been selected then the operation of bits 9:7 is the same as the external tx rxb, enable1 and enable2 pins respectively. 2.5 gsm/edge baseband control register - address 7 this register is only used when in gsm/edge mode. the bb gain bits enable the gsm baseband gain section to be reduced in 3 db increments. the nominal gain is 35 db (000). the i and q offset bits allow the gam baseband dc offset to be cancelled. <13> <12> <11> gain (db) 000 0 001 3 010 6 011 9 100 12 register bit no. action if '0' action if '1' 9 receive register (0) selected transmit register (1) selected 8 enable2 configuration register (3) selected 7 enable1 configuration register (2) selected 6 txrxb pin (34) selected serial bus selected - bit 9 5 enable2 pin (20) selected serial bus selected - bit 8 4 enable1 pin (11) selected serial bus selected - bit 7 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0111 oe bb gain q offset i offset address
zl20250 data sheet 38 zarlink semiconductor inc. 2.5.1 q channel gain adjust bits 22:20 adjust q channel gain. 2.5.2 baseband offset correction bits 19:12 adjust the dc offset for the q channel. bit 19 is the sign bit and bit 12 the lsb. bits 11:4 adjust the dc offset for the i channel with bit 11 the sign bit and bit 4 the lsb. the coding is the same for both i and q channels and is shown below: bit 23 must be set to '1' to enable dc offset correction. 2.6 test mode register - address 8 this register is used for test purposes only and should not be used. <22> <21> <20> gain adjustment(db) 000 0 001 -3 010 -6 011 -9 100 -12 101 -15 110 -18 111 -21 00000000 maximum positive correction 00000001 01111110 01111111 zero positive correction 11111111 zero n egative correction 11111110 10000001 10000000 maximum negative correction
zl20250 data sheet 39 zarlink semiconductor inc. 2.7 uhf pll divider programming register - address 9 bits 23:11 set m counter value (bit 23 = msb) bits 10:8 set b counter value - max value = 7 (bit 10 = msb) bits 7:4 set a counter value - max value = 7 (bit 6 = msb) the a counter is a 4 bit counter to enable correct fractional n operation. valid values of a are in the range 1 to 8. using the 64/65/72/73 four modulus prescaler the divide ratio (n) is given by: n = 64 * m + 8 * b + a values of m, b, a can be easily calculated using the formulae in the synthesizer section. 2.8 uhf pll reference divider and fractional n programming register - address 10 bit 23 is unused and should be set to '0' bits 22:18 set the fractional n numerator (bit 22 = msb) bits 17:4 set the reference counter value (bit 17 = msb) 2.9 receive vhf pll divider programming register - address 11 bits 23:21 are unused and should be set to '0' bits 20:8 set m counter value (bit 20 = msb) bits 7:4 set a counter value - max value = 15 (bit 7 = msb) using the 16/17 two modulus prescaler the divide value (n) is given by: n = 16 * m + a values of m, a can be easily calculated using the formulae in the synthesizer section, however the programming register has been organized to simplify this. 23222120191817161514131211109876543210 0 1001 m counter value b counter value x a counter value address 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1010 x frac n numerator uhf pll reference counter value address 232221201918171615141312111098 7 6 5 4 3210 000 1011 x x x m counter value a counter value address
zl20250 data sheet 40 zarlink semiconductor inc. for example for a divide ratio of 13235, the binary equivalent is: 11001110110011. the programming values can be selected as shown below: 2.10 receive vhf pll reference divider programming register - address 12 bits 23:19 are unused and should be set to '0' bit 18 selects common reference divider for vhf receive and transmit plls ('0' to select). if a common reference divider is selected then the transmit vhf reference divider is used which must be programmed in register 13. bits 17:4 set the reference divider value (bit 17 = msb) 2.11 transmit vhf pll divider programming register - address 13 bits 23:21 are unused and should be set to '0' bits 20:8 set m counter value (bit 20 = msb) bits 7:4 set a counter value - max value = 15 (bit 7 = msb) programming is identical to that for the receive vhf pll register 11. 2.12 transmit vhf pll reference divider programming register address 14 bits 23:18 are unused and should be set to '0' bits 17:4 set the reference counter value (bit 17 = msb) 2.13 pll lock detect & fractional n compensation programming register address 15 bit no. 20 19 18 17 16 15 14 13 12 11 10987654 count value 00011001110 110011 ma 2322212019 18 17161514131211109876543210 00000 1100 xxxxxrs receive vhf pll reference counter value address 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 1101 x x x m counter value a counter value address 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000000 1110 x x x x x x transmit vhf pll reference counter value address 23222120191817161514131211109876543210 1111 fractional n compensation uhf pll lock count transmit vhf pll lock count receive vhf pll lock count address
zl20250 data sheet 41 zarlink semiconductor inc. 2.13.1 fractional n compensation bits 23:16 set the value for fractional n compensation in the uhf pll with bit 23 as msb. the value for the compensation is dependent on a number of parameters which are described in the synthesizer section. 2.13.2 pll lock detect counters these 4 bit counters count the consecutive comparison cycles where the lock detect circuit gives an in-lock result. when the counter reaches its programmed count then that pll is deemed to have achieved full lock. this prevents spurious false in-lock signals while the pll is achieving lock up. there are separate counters for the uhf, rx vhf and tx vhf plls which are programmed as shown above. bits 15,11,7 are the msb's for the uhf, rx vhf and tx vhf pll lock detector counters respectively. a non zero value must be programmed for the lock detect to operate correctly. 3.0 absolute maximum ratings this device is sensitive to esd. most pins have an esd rating greater than 2000v (human body model hbm), however some pins have limited protection (800 to 2000v )in order to meet the rf performance. anti-static precautions should be used when handling this device. 4.0 operating conditions device operation is guaranteed under the following coonditions: supply voltage -0.3 to 3.6v voltage applied to any pin -0.3 to vcc + 0.3 v operating temperature -40c to 85c storage temperature -55c to 125c max junction temperature 125c condition min value typ max units comments general supply voltage 2.7 3.3 v operating temperature -40 +85 c logic input voltage high ? vih 0.8vcc volts logic input voltage low ? vil 0.2vcc volts tcxo reference frequency frequency 13.0 mhz gsm frequency 14.4 mhz is136 frequency 19.44 mhz is136
zl20250 data sheet 42 zarlink semiconductor inc. receiver receiver if frequency 70 215 mhz transmitter transmit if frequency 50 215 mhz i & q common mode voltage 1.2 v i & q input voltage level 1.5 v p-p 0db input buffer gain cellular band lo input level -15 -10 -5 dbm pcs band lo input level -15 -10 -5 dbm cellular band lo frequency 900 1100 pcs1900 band frequency 1900 2200 mhz serial control timing see figure 14 sdata set up t1 20 ns sdata hold t2 20 ns sclk pulse width t3 50 ns slatch set up t4 20 ns serial control timing (cont?d) slatch pulse width t5 50 ns sclk period t6 100 ns power control set up t7 20 ns condition min value typ max units comments
zl20250 data sheet 43 zarlink semiconductor inc. 5.0 electrical characteristics the electrical characteristics are guaranteed under the following conditions unless stated otherwise. vcc =3.0 v, t = 25c, tcxo ref frequency = 19.44 mhz. characteristics min value typ max units comments supply current sleep 10 40 a logic inputs = 0v or vcc receive operation amps 32 38 ma note 1, agc = 1.6v is136 33 39 ma note 1, agc = 1.6v gsm/edge 30 36 ma note 1, agc = 1.6v transmit operation 900 mhz output 141 170 ma vga = 2.4v, note 2 106 125 ma vga = 1v , note 2 1900 mhz output 120 145 ma vga = 2.4v, note 2 102 120 ma vga = 1v, note 2 standby operation uhf pll 12.5 15.0 ma note 3 receive vhf pll 5.2 6.3 ma transmit vhf pll 4.9 6.0 ma additional circuits frequency doubler 4 5 ma note 4 uhf lo output buffer 4.5 5.5 ma 900 or 1900 band note 5 logic inputs input current 10 na vin = 0 to vcc input capacitance 10 pf lock detect output
zl20250 data sheet 44 zarlink semiconductor inc. output voltage low 0.2vcc volts i out = 1ma output voltage high 0.8vcc volts i out = -1 ma tcxo input input resistance 10 k ? input capacitance 10 pf input sensitivity 0.5 2 v p-p ac coupled receiver - is136 all parameters are measured at an if frequency of 135.06 mhz, rx vco = 270 mhz unless stated otherwise input impedance 500 1500 ? max voltage gain 80 91 db agc = 2.4 v min voltage gain -13 5 db agc = 0.3 v gain slope 50 56 62 db/v agc = 0.3 to 2v nf gainmax 8 db rs =800 ? input v1db gainmin 101 104 db v minimum gain iip3 gainmax 74 db v max gain i/q amplitude matching +/- 0.5 db i/q quadrature accuracy +/- 2 output 1db compression 3 v p-p output dc offset +/-20 mv receiver amps (fixed gain) all parameters are measured at an if frequency of 135.06 mhz, rx vco = 270 mhz unless stated otherwise. vagc = 1.6v (gain 20 db below maximum) input impedance 500 1500 ? input sensitivity 14 db v note 6 noise figure 12 db input ip3 93 db v characteristics min value typ max units comments
zl20250 data sheet 45 zarlink semiconductor inc. audio output 900 1000 1100 mv note 7 rssi dynamic range 50 db accuracy -3 +3 db rssi slope 16 mv/db input signal - min 25 db v input signal - max 75 db v min rssi level 0.35 0.5 0.70 max rssi level 1.45 1.55 1.65 v rssi output impedance 1 k ? bandpass filter is136 and amps narrow bandwidth mode centre frequency 60 khz 3db bandwidth +/- 16 +/- 18 khz stop band attenuation relative to signal at 60khz 0 to 3 khz 67 69 db 3 khz to 10 khz 61 63 db 10 khz to 22 khz 48 51 db 38 khz 18 20 db 82 khz 18 20 db 98 khz to 110 khz 48 50 db 110 khz to 117 khz 61 63 db 117 khz to 123 khz 68 70 db 123 khz to 1.36 mhz 71 73 db 1.36 mhz to 1.52 mhz 36 48 db 1.52 mhz to 10 mhz 71 73 db image attenuation 0 to -10khz 61 db -10 khz to -42 khz 40 db characteristics min value typ max units comments
zl20250 data sheet 46 zarlink semiconductor inc. - 42 khz to -78 khz 30 40 db - 78 khz to -105 khz 40 db -105 khz to -1.36 mhz 61 db -1.36 mhz to -1.52 mhz 36 48 db -1.52 mhz to -10 mhz 61 db gain ripple 1.0 1.5 db 60khz +/- 12.5khz receiver - gsm all parameters are measured at an if frequency of 135.0 mhz, rx vco = 270 mhz unless stated otherwise. tcxo = 13.0mhz. if frequency 70 215 mhz input impedance 500 1500 ? max voltage gain 80 91 db agc = 2.4 v min voltage gain -13 +5 db agc = 0.3 v gain slope 50 56 62 db/v agc = 0.3 to 2v nf gainmax 8 db rs =800 ? input v1db gainmin 100 104 db v minimum gain iip3 gainmax 73 db vmax gain baseband filter attenuation 100khz 1 db 315khz 15 db 600khz 30 db 10mhz 60 db filter ripple 1 db 0 to 100khz output dc offset 10 20 mv after offset calibration. maximum base band gain i/q amplitude matching +/- 0.5 db i/q quadrature accuracy +/- 2 output 1db compression 3 v p-p characteristics min value typ max units comments
zl20250 data sheet 47 zarlink semiconductor inc. baseband gain adjust -21 0 db 3db steps baseband gain step resolution 3 db transmitter all parameters are measured at an if frequency of 180.0 mhz, tx vco = 360 mhz unless stated otherwise i & q modulator i/q input buffer gain -1 0 +1 db i/q input buffer gain 3 db i/q input buffer gain 6 db i/q input buffer gain 9 db i/q input buffer gain 12 db i & q differential input resistance 80 k ? i & q baseband filter attenuation (is136/amps) dc - 12.5 khz 0.5 db 85 - 180 khz 12 17 db > 180 khz 25 33 db i & q baseband filter attenuation (gsm/edge) dc to 100khz 1 db > 4mhz 55db db carrier suppression 30 40 db sideband suppression 30 40 db if variable gain amplifiers gain control range 45 60 db control voltage for minimum gain 0.10 v control voltage for maximum gain 2.4 v agc control voltage slope 33 38 43 db/v vga = 0.5 to 1.2v characteristics min value typ max units comments
zl20250 data sheet 48 zarlink semiconductor inc. if output filter (option) if output impedance 500 ? to external filter if input impedance 1.5 k ? from external filter if output level 100 mv 800mhz rf output stage specifications assume 50 ohm load driven via a matching network. output frequency = 836 mhz, uhf lo = -10 dbm at 1016 mhz. rf amplifier operating frequency range 824 849 mhz output power +8 +10 dbm acpr (tdma) -36 dbc pout = +8dbm, offset = 30khz -56 dbc pout = +8dbm, offset = 60khz output power amps +10 +14 dbm receive band noise (869 - 894 mhz) -124 dbm/hz ftx = 849 mhz pout = +8dbm with external if filter spurious outputs lo leakage -25 -21 dbc pout = +8dbm image rejection -27 -21 dbc pout = +8dbm other spurii -20 dbm 1900mhz rf output stage (pcs) specifications assume 50 ohm load driven via a matching network output frequency = 1880 mhz, uhf lo = -10 dbm at 2060 mhz. rf amplifier operating frequency range 1.88 1.91 ghz output power +8 +10 dbm acpr (tdma) -36 dbc pout = +8dbm, offset = 30khz -56 dbc pout = +8dbm, offset = 60khz characteristics min value typ max units comments
zl20250 data sheet 49 zarlink semiconductor inc. receive band noise (1930-1990 mhz) -128 dbm/hz ftx = 1910 mhz, pout = +8dbm with external if filter spurious outputs lo leakage -30 -25 dbc pout = +8dbm image rejection -30 -25 dbc pout = +8dbm other spurii -20 dbm uhf synthesiser input frequency 800 2200 mhz charge pump current 0.9 1 1.1 ma 0.45 0.5 0.55 ma 0.22 0.25 0.28 ma 0.11 0.125 0.14 ma charge pump output compliance 0.4 vdd - 0.4 v less than +/-10 % variation in iout charge pump sink/source mismatch 15 % charge pump off-state current 5 na fractional compensation 88 98 108 a full scale uhf buffers load impedance 200 ? output level (900 and 1900) -11 dbm load = 200 ohms harmonic level -40 dbc lo1900 output rx and tx if synthesisers input frequency 100 430 mhz charge pump current 0.9 1 1.1 ma 0.45 0.5 0.55 ma 0.22 0.25 0.28 ma 0.11 0.125 0.14 ma characteristics min value typ max units comments
zl20250 data sheet 50 zarlink semiconductor inc. note 1: all receive currents include all receiver sections plus rx vhf and uhf pll's, and uhf lo input buffer circuits. the lo o utput buffer and frequency doubler are not included. note 2: all transmit currents include all transmit sections plus tx vhf and uhf pll's, and uhf lo input buffer circuits. the lo output buffer and frequency doubler are not included. note 3: includes uhf lo input buffer note 4: this is only applicable in 1900 mhz band note 5: the uhf lo output buffer need only be powered up if required to drive an external circuit, for example, a receive front end mixer. note 6: input signal fm modulated with 8 khz deviation by 1 khz modulating signal. specification is minimum input level to obtai n 12 db sinad at fm output (pin 45) using ccitt filter. note 7: input modulation: 1khz modulating signal with 8 khz deviation. output level at fm out (pin 45) is set by external compon ents. see application section for details. charge pump output compliance 0.4 vcc - 0.4 v less than +/-10 % variation in iout charge pump sink/source mismatch 15 % charge pump off-state current 5 na rx lo oscillator frequency 140 430 mhz phase noise -99 dbc/hz freq = 270 mhz, offset = 30 khz tx lo oscillator frequency 260 430 mhz phase noise -99 dbc/hz freq = 360 mhz, offset = 30 khz characteristics min value typ max units comments
zl20250 data sheet 51 zarlink semiconductor inc. 6.0 typical performance curves 6.1 receive amps rx. - icc v temperature 29 30 31 32 33 34 35 36 37 38 -40 25 85 temperature c ma vcc = 2.7v vcc = 3.0v vcc = 3.3v is136 rx. - icc v temperature 27 28 29 30 31 32 33 34 35 -40 25 85 temperature c ma vcc = 2.7v vcc = 3.0v vcc = 3.3v rx. gain v agc (vcc) -20 0 20 40 60 80 100 120 0123 agc volts db vcc = 2.7v vcc = 3.0v vcc = 3.3v rx. gain v agc (temperature) -20 0 20 40 60 80 100 120 0123 agc volts db t = -40c t = 25c t = 85c
zl20250 data sheet 52 zarlink semiconductor inc. 6.2 transmit rx . rssi 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -150 -100 -50 0 input level dbm rssi voltag e -40c 25c 85c is136 tx. 900 mhz - icc v agc (temperature) 0 20 40 60 80 100 120 140 160 180 0123 a gc volts icc ma -40c 25c 85c is136 tx. 900 mhz - icc v agc (vcc) 0 20 40 60 80 100 120 140 160 180 0123 a gc volts icc ma vcc = 2.7v vcc = 3.0v vcc = 3.3v
zl20250 data sheet 53 zarlink semiconductor inc. is136 tx. 1900 mhz - icc v agc (vcc) 0 20 40 60 80 100 120 140 160 0123 a gc volts icc ma vcc = 2.7v vcc = 3.0v vcc = 3.3v is136 tx.1900 mhz - icc v agc (temperature) 0 20 40 60 80 100 120 140 160 0123 a gc volts icc ma -40c 25c 85c is136 tx. 900 mhz - power out v agc (vcc) -60 -50 -40 -30 -20 -10 0 10 20 0123 agc volts dbm vcc = 2.7v vcc = 3.0v vcc = 3.3v is136 tx. 900 mhz - power out v agc (temp.) -60 -50 -40 -30 -20 -10 0 10 20 0123 agc volts dbm -40c 25c 85c
zl20250 data sheet 54 zarlink semiconductor inc. is136 tx. 1900 mhz - power out v agc (vcc) -60 -50 -40 -30 -20 -10 0 10 20 0123 a gc volts dbm vcc = 2.7v vcc = 3.0v vcc = 3.3v is136 tx 1900mhz - power out v agc (temp.) -60 -50 -40 -30 -20 -10 0 10 20 0123 a gc volts dbm -40c 25c 85c
c zarlink semiconductor 2002 all rights reserved. apprd. issue date acn package code previous package codes l 1 211130 16jun01 213841 12dec02 2
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